FPGA Design Archives

UART frames consist of a start bit, data bits, an optional parity bit, and stop bit(s). Parity can be even, odd, or omitted. Even parity is calculated by ensuring an even total of 1s. The receiver checks the parity bit against calculated values to detect errors, flagging discrepancies accordingly.

yj

8월 22nd, 2025

FPGA Implementation of RoCEv2

What is the RoCE v2? RoCEv2, or RDMA over Converged […]

yj

8월 22nd, 2025

High Speed Serial Communication with AMD’s Gigabit Transceiver

What is the High Speed Serial Communication? High-speed serial communication […]

yj

8월 22nd, 2025

AXI with FPGA and SoC

AXI, or Advanced eXtensible Interface, is part of the AMBA protocol by ARM, designed for high-performance system designs in FPGAs and SoCs. It includes interfaces like AXI4, AXI4-Lite, and AXI4-Stream, each serving specific purposes. AXI channels facilitate reliable data transfer, underpinning efficient hardware design essential in modern applications.

yj

8월 22nd, 2025

Gigabit Ethernet with Xilinx FPGA and TEMAC IP

provides an overview of implementing Gigabit Ethernet using Xilinx FPGAs and the TEMAC IP core.

yj

[카테고리:] FPGA Design

고속통신에서 Scrambling(스크램블링) 의 역할

Line Coding (8B/10B)

병렬에서 고속 SERDES까지, 그리고 Gigabit Transceiver

High Speed Interface (10G, 100G) Guide

LeNet-5 FPGA 구현 가이드

UART Parity Bit and Frame Structure

FPGA Implementation of RoCEv2

High Speed Serial Communication with AMD’s Gigabit Transceiver

AXI with FPGA and SoC

Gigabit Ethernet with Xilinx FPGA and TEMAC IP

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