AXI stands for Advanced eXtensible Interface. It is a part of the AMBA (Advanced Microcontroller Bus Architecture) protocol family, developed by ARM. AXI is designed for high-performance, high-frequency system designs and is widely adopted in FPGAs and SoCs.
- Zynq SoC connects between Processing System (PS) and Programmable Logic (PL)
- Interconnection between Xilinx IP cores (e.g., Block RAM, DMA, TEMAC)
- Communication with MicroBlaze processor
- AXI Interconnect to connect multiple master/slave devices
Types of AXI Interfaces
| Type | Description | Use Case |
|---|---|---|
| AXI4 | Full-featured, supports burst transfers | Memory-mapped interfaces (e.g., DDR) |
| AXI4-Lite | Lightweight, no burst support | Control and configuration registers |
| AXI4-Stream | No address phase, continuous data flow | High-speed streaming (video, audio) |
When working with Xilinx IP cores, you’ll often use one or more of these AXI interfaces, depending on your system needs.
The AXI Channels
AXI4 and AXI4-Lite interfaces are composed of the following independent channels:
- Write Address Channel (AW*)
- Write Data Channel (W*)
- Write Response Channel (B*)
- Read Address Channel (AR*)
- Read Data Channel (R*)
- Read Response Channel (RRESP)
Each channel uses VALID/READY handshake signals to transfer data reliably. This enables pipelining and parallelism, essential for high-performance designs.
AXI4 (Memory Mapped)
AXI4 Memory-Mapped (AXI4-MM) is designed for high-performance memory-mapped communication between a master (e.g., CPU, DMA) and a slave (e.g., memory, custom IP).
| Signal | Direction | Description |
|---|---|---|
awaddr | Master → Slave | Write address |
awvalid | Master → Slave | Write address valid |
awready | Slave → Master | Write address accepted |
wdata | Master → Slave | Write data |
wvalid | Master → Slave | Write data valid |
wready | Slave → Master | Write data accepted |
bresp | Slave → Master | Write response (OKAY, SLVERR, etc) |
bvalid | Slave → Master | Write response valid |
bready | Master → Slave | Master ready to receive response |
araddr | Master → Slave | Read address |
arvalid | Master → Slave | Read address valid |
arready | Slave → Master | Read address accepted |
rdata | Slave → Master | Read data |
rvalid | Slave → Master | Read data valid |
rready | Master → Slave | Master ready to accept read data |
rresp | Slave → Master | Read response (OKAY, SLVERR, etc) |
Write Transaction
- Master sends write address over AW channel
- Master sends write data over W channel
- Slave send write response over B channel
Read Transaction
- Master sends read address over AR channel
- Slave send read data the response over R channel
Key Features
| Feature | Description |
|---|---|
| Address-based | All data transactions use memory addresses |
| Supports bursts | Up to 256 data beats per burst |
| Separate channels | Independent channels for address, data, and responses |
| Out-of-order support | Responses can come back out-of-order |
AXI4-Lite
AXI4-Lite is a lightweight version of the AXI4 protocol, used for low-throughput control interfaces. It is typically used for accessing control and status registers in IP cores.
Key Features
- No burst, only single data transfers
- Lower logic and routing resource usage
- Ideal for control/status register access
- Master (e.g., CPU) configures slave IP core
| Feature | AXI4-MM | AXI4-Lite |
|---|---|---|
| Burst Transfers | ✅ Supported | ❌ Not supported |
| Max Transfer Size | Up to 256 beats | 1 beat |
| Complexity | Higher | Lower |
| Use Case | High data transfer | Control registers |
AXI Stream
AXI4-Stream is a simplified AXI protocol designed to transmit raw data without addressing. It is optimized for high-throughput, continuous data transfer, such as video, audio, or network packets.
Features
- No address channel-simple interface
- Handshake using TVALID and TREADY
- Pipelined structure for high speed
- Supports TKEEP, TLAST, TUSER for flexibility
| Signal | Description |
|---|---|
| TVALID | Sender indicates valid data |
| TREADY | Receiver is ready to accept data |
| TDATA | Actual data being transmitted |
| TLAST | Marks the end of a frame or packet |
| TKEEP | Byte qualifier for which bytes in TDATA are valid |
| TUSER | Optional user-defined signal |
When TVALID is high and TREADY is high, a data transfer occurs on the TDATA bus. This handshake ensures safe and synchronized data transmission.
AXI is the de facto standard interface in modern FPGA and SoC designs. A good understanding of AXI is essential for efficient and scalable hardware design.
Below is the link to the AXI website: https://www.arm.com/architecture/system-architectures/amba/amba-specifications